基于扰动Delta-sigma调制器的小数分频器

Fractional Frequency Divider Based on Dithered Delta-sigma Modulator

中文关键词:  宽带  2/3 分频器  扰动  Delta-sigma 调制器

英文关键词:wide-band  2/3 frequency divider  dither  Delta-sigma modulator

中文摘要:

      文中基于扰动Delta-sigma调制器分析并设计了一款动态分频比控制的宽带小数分频器链路。其中,整数分频 器链路由高速2分频器和7级2/3分频器链路级联构成,小数控制部分由外加扰动的Delta-sigma 调制器构成。通过理论分 析和仿真表明,合理选择扰动信号的添加位置,可以有效延长Delta-sigma 调制器的输出序列长度,从而平滑Delta-sigma 调制 器的输出频谱。该分频器电路采用TPS 65 nm 射频绝缘体上硅(RFSOI)互补金属氧化物半导体(CMOS)工艺制造,包括焊盘 在内的芯片面积为0. 57 mm2。测试结果表明,该小数分频器链路在1.2 V 的供电电压下,最大工作电流为22.2 mA,可以在 9 GHz~20 GHz 的输入频率下动态加载控制字并实现小数分频功能。

英文摘要:

      Based on the dithered Delta-sigma modulator, in this paper a wide-band fractional frequency divider with dynamic division ratio is analyzed and designed. The integer frequency divider is composed of high-speed divide-by-2 frequency divider and 7-stage 2/3 frequency divider chain cascade, and the fraction control circuit is composed of the Delta-sigma modulator with an additive dither signal. Theoretical analysis and simulation show that, selecting the adding position of the dither signal appropriately can extend the output sequence length effectively, so as to smooth the output spectrum of the Delta-sigma modulator. The divider is manufactured by TPS 65 nm radio-frequency silicon-on-insulator ( RFSOI) complementary metal oxide semiconductor ( CMOS) process, and the chip area including the pad is 0. 57 mm2. The measured results show that the maximum operating current of the fractional frequency divider chain is 22. 2 mA with the supply voltage of 1. 2 V. The chip can dynamically load the control word and realize the function of frequency division with the input frequency at the range from 9 GHz to 20 GHz.